1. Field of the Invention
The present invention is broadly concerned with a digital signal processing unit that runs a bit serial operation, and intended particularly for technology to minimize the circuit scale for the bit serial, digital signal processing. More specifically this invention is applied to a data compressing and expanding device. One of the embodiments of the invention is the compressing and expanding device for image data. Exemplary applications of the invention include a wide variety of image equipment, for example, electronic cameras and visual telephones.
2. Description of the Related Art
Digital signal processing technology has conventionally been adopted in various industrial and other fields.
In the arena of speech and image processing, for instance, digital filters and digital compressing and expanding devices (orthogonal transformation) have been utilized in varied activities.
This sort of digital signal processing is however disadvantageous in that, when effected in parallel operation, it is compelled to increase the largeness of the circuitry concerned; the fact which led to the development of the digital signal processing by way of bit serial computation.
In this type of digital signal processing unit relying on the bit serial computation, the multiplication by addition of power of 2 of a given coefficient is performed through a combination of a shift register (coupled flip-flops) and adder/subtracter. This results naturally in elimination of the multiplier needed in the parallel computation. The numerical accuracy of such a bit serial operation depends largely upon the number of stages in the shift register (flip-flops).
Discrete Cosine Transform (DCT) is one of the branches of the digital signal processing that have lately arrested public attention. This is an orthogonal transform whose defining equations are as indicated in Eq. 1 and Eq. 2, the Eq. 1 being for Forward Discrete Cosine Transform (FDCT) and Eq. 2, Inverse Discrete CosineTtransform (IDCT). ##EQU1##
Several fast computation algorithms for the DCT have been studied, and one of them is described in IEEE Transaction on Communications, Vol. COM-25, No. 11, November, 1977, (Adaptive Coding of Monochrome and Color Image, Wen-Hsiung Chen and C. Harrison Smith.) Japanese Unexamined Patent Hei 3-145274 proposes a bit serial operation comformable to the DCT flow which is described in the document mentioned above.
Although the adoption of the bit serial computation in the digital signal processing may reduce markedly the circuitry size involved as has thus far been explained, relatively longer time required for the serial computation had elicited the necessity of further improvements.
Moreover the direct application of high-speed algorithm into some hardware still manifested, to a pronounced degree, the largeness of the circuitry concerned as has been described in the foregoing official gazette, which also meant the requirement of yet further enhancements.
In addition the signal processing unit running the bit serial computation necessitates in its prior stage, a parallel to serial converter. A serial to parallel converter should therefore be provided in the posterior stage of the signal processing unit in order to transform the data resulting from the above bit serial operation into so many parallel information. Such auxiliary circuit making the total system even still larger, there arose a requisite for yet other ameliorations.